1. Field of the Invention
The present invention relates to analog-to-digital converters having a first reference potential source for providing first reference potentials, a first input stage having at least two differential amplifiers. Each of the differential amplifiers have a first and second transistor, a first input for feeding in one of the reference potentials, a second input for feeding in a first input signal, and two output terminals.
2. Description of the Related Art
An analog-to-digital converter (A/D converter) of this type is disclosed for example in Hui Pan et al.: xe2x80x9cA3.3V 12b 50Msample/s A/D Converter in 0.6 xcexcm CMOS with over 80 dB SFDRxe2x80x9d, paper MP 2.4, Proceedings of the International Solid State Circuit Conference ISSCC 2000. FIG. 1 illustrates an input stage of such an A/D converter according to the prior art.
This A/D converter has as reference potential source, a series circuit of resistors R11, R12, R13, R14, R15 which are connected up between a supply potential Vdd and a reference-ground potential GND. In this case, different reference potentials VRP1, VRP2, VRP3, VRP4 can be tapped off in each case at nodes between two adjacent resistors. These reference potentials VRP1, VRP2, VRP3, VRP4 are fed to respective first inputs of identically constructed differential amplifiers DV11, DV12, DV13, DV14, a first input signal VIP being fed to second inputs of these differential amplifiers DV11, . . . , DV14. The differential amplifiers DV11, . . . , DV14 each have first and second transistors T11, T12, the gate terminal of the first transistor T11 being connected to a first input terminal E11 of the differential amplifier and the gate terminal of the second transistor T12 being connected to a second input terminal E12. Source terminals of the first and second transistors of the differential amplifier DV11, . . . , DV14 are connected to a common current source I11. The drain terminals of the first and second transistors T11, T12 form output terminals A11, A12 of the differential amplifiers DV11, . . . , DV14, these output terminals A11, A12 being connected to a second supply potential V+ via resistors RL1, RL2, for example. By means of comparators (not specifically illustrated), the potentials at the two output terminals A11, A12 of a differential amplifier are evaluated, and the first input signal VIP is compared with all the reference potentials VRP1, . . . , VRP4 in this way.
The A/D converter known according to the prior art and illustrated in FIG. 1 has a second input stage in addition to the first input stage. This second input stage has a series circuit of resistors R21, R22, R23, R24, which are connected up between the supply potential Vdd and the reference-ground potential GND. In this case, reference potentials VRM1, VRM2, VRM3, VRM4 can be tapped off at nodes between the resistors R21, . . . , R24 and are fed to respective first inputs of differential amplifiers DV21, DV22, DV23, DV24. These differential amplifiers DV21, . . . , DV24 are identical to one another and identical to the differential amplifiers DV11, . . . , DV14 of the first input stage. A second input signal VIM, which corresponds to the difference between a constant signal and the input signal VIP, is fed to the second input terminal of the differential amplifiers DV21, . . . , DV24 of the second input stage. A differential amplifier of the first input stage and a differential amplifier of the second input stage in each case form a differential amplifier pair, in which the first output A11 of a differential amplifier DV11 of the first input stage is connected to the second output A22 of a differential amplifier DV21 of the second input stage and a second output A12 of a differential amplifier DV11 of the first input stage is connected to a first output A21 of a differential amplifier DV21 of the second input stage. In this case, the common outputs M1, P1 are connected to the second supply potential V+ via resistors RL1, RL2. The reference potentials VRM1, . . . , VRM4 fed to the differential amplifiers DV21, . . . , DV24 of the second input stage correspond to the difference between the first supply potential Vdd and the supply potential VRP1, VRP2, VRP3, VRP4 of the associated differential amplifier DV11, . . . , DV14 of the first input stage. This combination of two differential amplifiers to form a differential amplifier pair, complementary input signals VIP, VIM and complementary reference potentials VRP1, . . . , VRP4, VRM1, . . . , VRM4 in each case being fed to the individual differential amplifiers of a differential amplifier pair, increases the common-mode rejection of such an A/D converter according to the prior art.
In order to be able to operate the transistors of the differential amplifiers in the known A/D converter in the saturation region, a minimum gate potential is required for driving them, which results from the sum of the saturation voltage of the current source, the threshold voltage, that is to say the gate-source voltage at which the transistors start to conduct, and an effective gate voltage. When the transistors are realized as n-channel MOS transistors and the current sources are also realized as MOS transistors using silicon technology, typical values are 0.15 V for the saturation voltage of the current source, 0.3 V for the threshold voltage and 0.15 V for the required effective gate voltage, with the result that the gate potential at the transistors must be a minimum of 0.6 V in order to be able to operate the transistors of the differential amplifiers in the saturation region. In other words, the respective smallest reference potential (VRP1, VRM4 in FIG. 1) must be at least 0.6 V. If a supply voltage of 1.2 V is assumed for an entire circuit arrangement in which the A/D converter is realized, and if account is taken of the fact that driver stages for providing the input voltage VIP, VIM usually fall short by at least 0.2 V in attaining the supply voltage of 1.2 V, with the result that the maximum input voltage is only about 1.0 V, then a usable input voltage range remains within which the input signal VIP is permitted to fluctuate by only 0.4 V, which corresponds to one third of the supply voltage. Such a small input voltage range is not sufficient for many applications.
It is an aim of the present invention, therefore, to provide an analog-to-digital converter in which the processable voltage range of the input signal is increased compared with previously known analog-to-digital converters.
This aim is achieved with an A/D converter wherein first and second transistors of at least one of the differential amplifiers are of a type complementary to the first and second transistors of the other differential amplifiers.
Accordingly, the A/D converter according to the invention has a first reference potential source for providing first reference potentials, and a first input stage having at least two differential amplifiers, which each have a first and a second transistor. According to the invention, the first and second transistors of at least one differential amplifier are of a type complementary to the first and second transistors of the other differential amplifiers, in other words the first and second transistors of at least one differential amplifier are designed as p-channel transistors, while the first and second transistors of the other differential amplifiers are designed as n-channel transistors.
The advantage of using differential amplifiers having p-channel transistors and differential amplifiers having n-channel transistors in an A/D converter consists in the possibility of also being able to process input signals which lie below the minimum gate potential for n-channel transistors.